Wireless devices have been in use for many years for enabling mobile communication of voice and data. Such devices can include mobile phones and wireless enabled personal digital assistants (PDA's) for example. FIG. 1 is a generic block diagram of the core components of such wireless devices. The wireless core 10 includes a base band processor 12 for controlling application specific functions of the wireless device and for providing and receiving voice or data signals to a radio frequency (RF) transceiver chip 14. The RF transceiver chip 14 is responsible for frequency up-conversion of transmission signals, and frequency down-conversion of received signals. RF transceiver chip 14 includes a receiver core 16 connected to an antenna 18 for receiving transmitted signals from a base station or another mobile device, and a transmitter core 20 for transmitting signals through the antenna 18. Those of skill in the art should understand that FIG. 1 is a simplified block diagram, and can include other functional blocks that may be necessary to enable proper operation or functionality.
Generally, the transmitter core 20 is responsible for up-converting electromagnetic signals from base band to higher frequencies for transmission, while receiver core 16 is responsible for down-converting those high frequencies back to their original frequency band when they reach the receiver, processes known as up-conversion and down-conversion (or modulation and demodulation) respectively. The original (or base band) signal, may be, for example, data, voice or video. These base band signals may be produced by transducers such as microphones or video cameras, be computer generated, or transferred from an electronic storage device. In general, the high frequencies provide longer range and higher capacity channels than base band signals, and because high frequency radio frequency (RF) signals can propagate through the air, they are preferably used for wireless transmissions.
All of these signals are generally referred to as radio frequency (RF) signals, which are electromagnetic signals; that is, waveforms with electrical and magnetic properties within the electromagnetic spectrum normally associated with radio wave propagation.
In a typical radio of a wireless device, the radio operates at a specific bandwidth (BW) in MHz or chip rate in Msamples/s (Ms/s), and the wireless transceiver upconverts an output signal from the radio to another frequency for wireless transmission. For example in a 3G radio, where 3G is well known wireless communication standard, the BW is 3.84 MHz and the chip rate (also known as sample rate) is 3.84 Ms/s. In the example wireless device of FIG. 1, the output of base band processor 12 is provided at 3.84 Ms/s. Ideally, the transmitter core 20 operates with frequencies that are harmonics of 3.84 MHz, which persons of skill in the art would understand are straightforward to implement. In this example, an ideal clock in the chip would run at 38.4 MHz, which can be easily divided by 10 to yield 3.84 MHz.
Currently, an interface standard has been established for governing signal communication between a base band processor and the RF transceiver, called DigRF. DigRF is a digital interface standard defined and supported by the Mobile Industry Processor Interface (MIPI) Alliance, and should be well known to those of skill in the art. Under the DigRF standard, the base band processor creates the digital versions of I and Q data signals and sends them to the RF transceiver. The RF transceiver then performs digital-to-analog conversion to create the analog signals that become the radio signal to be transmitted. In the DigRF standard, transactions with the interface are conducted at a preset frequency of 312 MHz, or a sample rate of 312 Ms/s. Unfortunately, 312 MHz is not a harmonic of the 3.84 MHz chip rate from the base band processor. In otherwords, 3.84 MHz is not an integer multiple of 312 MHz.
This is problematic given that one of the requirements in DigRF 3G is to perform uplink RRC (root raised cosine) pulse shaping. For example, an input to the RRC pulse shaper should be running at the WCDMA chip rate of 3.84 Ms/s, while its output should be generating samples at a sample rate compatible with a digital to analog converter (DAC) of the transmit path of the RF transceiver. However, a suitable sample rate for a downstream DAC may not be a multiple 3.84 Ms/s.
One solution is to design the RF transceiver to generate a different clock that is some multiple of 3.84 MHz, however clock generation is relatively expensive to implement. Furthermore, on chip generated clock harmonics may fall in or out of the band spectrum.
It is, therefore, desirable to provide a system and method for sample rate conversion between frequencies that are not harmonics of each other.